1. Field of the Invention
The present invention relates to displays, and particularly to a power supply of a display.
2. Description of the Prior Art
Please refer to FIG. 1, which is a block diagram of a driving structure of a display 100. The display 100 includes an AC/DC converter 110, a pixel driving unit 120, a panel 130 having a plurality of pixels 131, a switching-type DC/DC converter 140, and a timing controller (Tcon) 150. The AC/DC converter 110 converts AC power to appropriate DC power, which is provided to the DC/DC converter 140. The DC/DC converter 140 converts the DC power provided by the AC/DC converter 110 to another DC power, which is provided to the pixel driving unit 120 for driving the pixels 131 arranged in a matrix. Moreover, the driving sequence of the plurality of pixels 131 is controlled by the timing controller 150, which generally includes two input units for receiving horizontal synchronization signal (Hsync) and vertical synchronization signal (Vsync), respectively.
Please refer to FIG. 2, which is a diagram of a switching-type boost DC/DC converter. The switching-type boost DC/DC converter 140 includes an input power source 210, a storage inductor 220, a diode 230, an output capacitor 240, a load 250, a switch 260, and a control unit 270. For generating a proper DC output voltage (Vo), the control unit 270 controls the switch 260 to turn ON and OFF such that the input power source 210 charges the storage inductor 220 via the current ION, then the power stored in the storage inductor 220 charges the output capacitor 240 via the current IOFF. Moreover, the control unit 270 can control the switch 260 by utilizing control modes including pulse width modulation (PWM) and pulse frequency modulation (PFM), for example.
Please refer to FIG. 1 to FIG. 3, where FIG. 3 is a diagram of driving waveforms of a power supply of related art. The waveforms in FIG. 3 include PWM switching voltage (VDS) 310, PWM output voltage (Vo) 320, PFM switching voltage (VDS) 330, PFM output voltage 340, and horizontal synchronization signal 350 and vertical synchronization signal 360 received by the timing controller 150. Please refer to the PWM switching voltage (VDS) 310. When the switch 260 is ON (short), the PWM switching voltage (VDS) 310 is at a low voltage level, and the input power source 210 charges the storage inductor 220 via the current ION. When the switch 260 is OFF (break), the PWM switching voltage (VDS) 310 is at a high voltage level, and the power stored in the storage inductor 220 charges the output capacitor 240 via the current IOFF. A high level gate-source voltage (VGS) can turn ON the switch 260, and a low level gate-source (VGS) voltage can turn OFF the switch 260 when the switch 260 is implemented with an N-type MOSFET, for example. Moreover, the control unit 270 controls the switch 260 for generating the output voltage without switching cooperatively with the horizontal synchronization signal 350 and the vertical synchronization signal 360.
Please refer to PFM switching voltage (VDS) 330. The PFM control mode is similar to the PWM control mode in the aspect of charging the storage inductor 220 and the output capacitor 240 in turn. In more detail, the difference is that the PFM control mode charges the storage inductor 220 and the output capacitor 240 a plurality of times with identical charging duration lengths. In one embodiment, the switch 260 can stay in an OFF state, so as not to recharge the storage inductor 220 even when the power stored in the storage inductor 220 is fully discharged. The switch 260 turns ON to charge the storage inductor 220 to prepare power to charge the output capacitor 240 until the output voltage (Vo) is lower than a predetermined value relative to a predetermined reference voltage.
U.S. Pat. No. 5,910,887 discloses a control method for a power supply of a display. Please refer to FIG. 7, which is a related PWM control waveform with cooperative switching with the horizontal synchronization signal. The waveforms in FIG. 7 include horizontal synchronization signal 701, original switch waveform 702 including PWM switching voltage (VDS) 7021 and storage inductor current 7022, switching noise 703, modified switch waveform 704 including modified PWM switching voltage (VDS) 7041 and modified storage inductor current 7042, and modified switching noise 705. In FIG. 7, reference number 706 indicates a horizontal blanking period, and reference number 707 indicates a horizontal active period. U.S. Pat. No. 5,910,887 discloses that the switch 260 can switch ON and switch OFF during two adjacent horizontal blanking periods 706, respectively. Moreover, U.S. Pat. No. 5,910,887 discloses that the switching mode can prevent the effect of the switching noise 703 when the display is refreshing. However, U.S. Pat. No. 5,910,887 does not take into consideration whether restricting the switching time of the power supply would still effectively keep the output voltage of the power supply at a reference voltage or not. In other words, restriction of the switching time of the power supply may lead to a high variance of the output voltage of the power supply, which would cause flicker or brightness variation of a display. Moreover, the issue of power savings is increasingly important due to applications to portable devices. The PFM control mode has the benefit of power savings. However, the control method disclosed in U.S. Pat. No. 5,910,887 cannot be applied to the PFM control mode.
Moreover, the display with DC/DC power supply using a traditional PFM control mode will exhibit a visible stripe in the displayed image when the switching frequency of the DC/DC power supply is low corresponding to a low power consumption condition. However, a higher switching frequency of the DC/DC power supply would lead to higher power consumption.